Method of and apparatus for forming three-dimensional structures integral with semiconductor based circuitry

ABSTRACT

Enhanced Electrochemical fabrication processes are provided that can form three-dimensional multi-layer structures using semiconductor based circuitry as a substrate. Electrically functional portions of the structure are formed from structural material (e.g. nickel) that adheres to contact pads of the circuit. Aluminum contact pads and silicon structures are protected from copper diffusion damage by application of appropriate barrier layers.

RELATED APPLICATIONS

[0001] This application claims benefit of U.S. Provisional PatentApplication No. 60/379,183, filed on May 7, 2002 which is herebyincorporated herein by reference as if set forth in full.

GOVERNMENT SUPPORT

[0002] This invention was made with Government support under GrantNumbers DABT63-97-C-0051 and DABT63-99-C0042 awarded by DARPA. TheGovernment has certain rights.

FIELD OF THE INVENTION

[0003] This invention relates to the field of electrochemical depositionand more particularly to the field of electrochemical fabrication whichincludes electrochemical deposition of one or more materials accordingto desired cross-sectional configurations so as to build upthree-dimensional structures from a plurality of at least partiallyadhered layers of deposited material. More particularly the inventionrelates to the integration of multilayer electrochemically fabricatedstructures with semiconductor circuitry and in particular to theformation of such structures on integrated circuits.

BACKGROUND

[0004] A technique for forming three-dimensional structures (e.g. parts,components, devices, and the like) from a plurality of adhered layerswas invented by Adam L. Cohen and is known as ElectrochemicalFabrication. It is being commercially pursued by MEMGen® Corporation ofBurbank, Calif. under the name EFAB™. This technique was described inU.S. Pat. No. 6,027,630, issued on Feb. 22, 2000. This electrochemicaldeposition technique allows the selective deposition of a material usinga unique masking technique that involves the use of a mask that includespatterned conformable material on a support structure that isindependent of the substrate onto which plating will occur. Whendesiring to perform an electrodeposition using the mask, the conformableportion of the mask is brought into contact with a substrate while inthe presence of a plating solution such that the contact of theconformable portion of the mask to the substrate inhibits deposition atselected locations. For convenience, these masks might be genericallycalled conformable contact masks; the masking technique may begenerically called a conformable contact mask plating process. Morespecifically, in the terminology of MEMGen® Corporation of Burbank,Calif. such masks have come to be known as INSTANT MASKS™ and theprocess known as INSTANT MASKING™ or INSTANT MASK™ plating. Selectivedepositions using conformable contact mask plating may be used to formsingle layers of material or may be used to form multi-layer structures.The teachings of the '630 patent are hereby incorporated herein byreference as if set forth in full herein. Since the filing of the patentapplication that led to the above noted patent, various papers aboutconformable contact mask plating (i.e. INSTANT MASKING) andelectrochemical fabrication have been published:

[0005] 1. A. Cohen, G. Zhang, F. Tseng, F. Mansfeld, U. Frodis and P.Will, “EFAB: Batch production of functional, fully-dense metal partswith micro-scale features”, Proc. 9th Solid Freeform Fabrication, TheUniversity of Texas at Austin, p161, August 1998.

[0006] 2. A. Cohen, G. Zhang, F. Tseng, F. Mansfeld, U. Frodis and P.Will, “EFAB: Rapid, Low-Cost Desktop Micromachining of High Aspect RatioTrue 3-D MEMS”, Proc. 12th IEEE Micro Electro Mechanical SystemsWorkshop, IEEE, p244, January 1999.

[0007] 3. A. Cohen, “3-D Micromachining by Electrochemical Fabrication”,Micromachine Devices, March 1999.

[0008] 4. G. Zhang, A. Cohen, U. Frodis, F. Tseng, F. Mansfeld, and P.Will, “EFAB: Rapid Desktop Manufacturing of True 3-D Microstructures”,Proc. 2nd International Conference on Integrated MicroNanotechnology forSpace Applications, The Aerospace Co., April 1999.

[0009] 5. F. Tseng, U. Frodis, G. Zhang, A. Cohen, F. Mansfeld, and P.Will, “EFAB: High Aspect Ratio, Arbitrary 3-D Metal Microstructuresusing a Low-Cost Automated Batch Process”, 3rd International Workshop onHigh Aspect Ratio MicroStructure Technology (HARMST '99), June 1999.

[0010] 6. A. Cohen, U. Frodis, F. Tseng, G. Zhang, F. Mansfeld, and P.Will, “EFAB: Low-Cost, Automated Electrochemical Batch Fabrication ofArbitrary 3-D Microstructures”, Micromachining and MicrofabricationProcess Technology, SPIE 1999 Symposium on Micromachining andMicrofabrication, September 1999.

[0011] 7. F. Tseng, G. Zhang, U. Frodis, A. Cohen, F. Mansfeld, and P.Will, “EFAB: High Aspect Ratio, Arbitrary 3-D Metal Microstructuresusing a Low-Cost Automated Batch Process”, MEMS Symposium, ASME 1999International Mechanical Engineering Congress and Exposition, November,1999.

[0012] 8. A. Cohen, “Electrochemical Fabrication (EFABTM)”, Chapter 19of The MEMS Handbook, edited by Mohamed Gad-EI-Hak, CRC Press, 2002.

[0013] 9. “Microfabrication—Rapid Prototyping's Killer Application”,pages 1-5 of the Rapid Prototyping Report, CAD/CAM Publishing, Inc.,June 1999.

[0014] The disclosures of these nine publications are herebyincorporated herein by reference as if set forth in full herein.

[0015] The electrochemical deposition process may be carried out in anumber of different ways as set forth in the above patent andpublications. In one form, this process involves the execution of threeseparate operations during the formation of each layer of the structurethat is to be formed:

[0016] 1. Selectively depositing at least one material byelectrodeposition upon one or more desired regions of a substrate.

[0017] 2. Then, blanket depositing at least one additional material byelectrodeposition so that the additional deposit covers both the regionsthat were previously selectively deposited onto, and the regions of thesubstrate that did not receive any previously applied selectivedepositions.

[0018] 3. Finally, planarizing the materials deposited during the firstand second operations to produce a smoothed surface of a first layer ofdesired thickness having at least one region containing the at least onematerial and at least one region containing at least the one additionalmaterial.

[0019] After formation of the first layer, one or more additional layersmay be formed adjacent to the immediately preceding layer and adhered tothe smoothed surface of that preceding layer. These additional layersare formed by repeating the first through third operations one or moretimes wherein the formation of each subsequent layer treats thepreviously formed layers and the initial substrate as a new andthickening substrate.

[0020] Once the formation of all layers has been completed, at least aportion of at least one of the materials deposited is generally removedby an etching process to expose or release the three-dimensionalstructure that was intended to be formed.

[0021] The preferred method of performing the selectiveelectrodeposition involved in the first operation is by conformablecontact mask plating. In this type of plating, one or more conformablecontact (CC) masks are first formed. The CC masks include a supportstructure onto which a patterned conformable dielectric material isadhered or formed. The conformable material for each mask is shaped inaccordance with a particular cross-section of material to be plated. Atleast one CC mask is needed for each unique cross-sectional pattern thatis to be plated.

[0022] The support for a CC mask is typically a plate-like structureformed of a metal that is to be selectively electroplated and from whichmaterial to be plated will be dissolved. In this typical approach, thesupport will act as an anode in an electroplating process. In analternative approach, the support may instead be a porous or otherwiseperforated material through which deposition material will pass duringan electroplating operation on its way from a distal anode to adeposition surface. In either approach, it is possible for CC masks toshare a common support, i.e. the patterns of conformable dielectricmaterial for plating multiple layers of material may be located indifferent areas of a single support structure. When a single supportstructure contains multiple plating patterns, the entire structure isreferred to as the CC mask while the individual plating masks may bereferred to as “submasks”. In the present application such a distinctionwill be made only when relevant to a specific point being made.

[0023] In preparation for performing the selective deposition of thefirst operation, the conformable portion of the CC mask is placed inregistration with and pressed against a selected portion of thesubstrate (or onto a previously formed layer or onto a previouslydeposited portion of a layer) on which deposition is to occur. Thepressing together of the CC mask and substrate occur in such a way thatall openings, in the conformable portions of the CC mask contain platingsolution. The conformable material of the CC mask that contacts thesubstrate acts as a barrier to electrodeposition while the openings inthe CC mask that are filled with electroplating solution act as pathwaysfor transferring material from an anode (e.g. the CC mask support) tothe non-contacted portions of the substrate (which act as a cathodeduring the plating operation) when an appropriate potential and/orcurrent are supplied.

[0024] An example of a CC mask and CC mask plating are shown in FIGS.1(a)-1(c). FIG. 1(a) shows a side view of a CC mask 8 consisting of aconformable or deformable (e.g. elastomeric) insulator 10 patterned onan anode 12. The anode has two functions. FIG. 1(a) also depicts asubstrate 6 separated from mask 8. One is as a supporting material forthe patterned insulator 10 to maintain its integrity and alignment sincethe pattern may be topologically complex (e.g., involving isolated“islands” of insulator material). The other function is as an anode forthe electroplating operation. CC mask plating selectively depositsmaterial 22 onto a substrate 6 by simply pressing the insulator againstthe substrate then electrodepositing material through apertures 26 a and26 b in the insulator as shown in FIG. 1(b). After deposition, the CCmask is separated, preferably non-destructively, from the substrate 6 asshown in FIG. 1(c). The CC mask plating process is distinct from a“through-mask” plating process in that in a through-mask plating processthe separation of the masking material from the substrate would occurdestructively. As with through-mask plating, CC mask plating depositsmaterial selectively and simultaneously over the entire layer. Theplated region may consist of one or more isolated plating regions wherethese isolated plating regions may belong to a single structure that isbeing formed or may belong to multiple structures that are being formedsimultaneously. In CC mask plating as individual masks are notintentionally destroyed in the removal process, they may be usable inmultiple plating operations.

[0025] Another example of a CC mask and CC mask plating is shown inFIGS. 1(d)-1(f). FIG. 1(d) shows an anode 12′ separated from a mask 8′that comprises a patterned conformable material 10′ and a supportstructure 20. FIG. 1(d) also depicts substrate 6 separated from the mask8′. FIG. 1(e) illustrates the mask 8′ being brought into contact withthe substrate 6. FIG. 1(f) illustrates the deposit 22′ that results fromconducting a current from the anode 12′ to the substrate 6. FIG. 1(g)illustrates the deposit 22′ on substrate 6 after separation from mask8′. In this example, an appropriate electrolyte is located between thesubstrate 6 and the anode 12′ and a current of ions coming from one orboth of the solution and the anode are conducted through the opening inthe mask to the substrate where material is deposited. This type of maskmay be referred to as an anodeless INSTANT MASK™ (AIM) or as ananodeless conformable contact (ACC) mask.

[0026] Unlike through-mask plating, CC mask plating allows CC masks tobe formed completely separate from the fabrication of the substrate onwhich plating is to occur (e.g. separate from a three-dimensional (3D)structure that is being formed). CC masks may be formed in a variety ofways, for example, a photolithographic process may be used. All maskscan be generated simultaneously, prior to structure fabrication ratherthan during it. This separation makes possible a simple, low-cost,automated, self-contained, and internally-clean “desktop factory” thatcan be installed almost anywhere to fabricate 3D structures, leaving anyrequired clean room processes, such as photolithography to be performedby service bureaus or the like.

[0027] An example of the electrochemical fabrication process discussedabove is illustrated in FIGS. 2(a)-2(f). These figures show that theprocess involves deposition of a first material 2 which is a sacrificialmaterial and a second material 4 which is a structural material. The CCmask 8, in this example, includes a patterned conformable material (e.g.an elastomeric dielectric material) 10 and a support 12 which is madefrom deposition material 2. The conformal portion of the CC mask ispressed against substrate 6 with a plating solution 14 located withinthe openings 16 in the conformable material 10. An electric current,from power supply 18, is then passed through the plating solution 14 via(a) support 12 which doubles as an anode and (b) substrate 6 whichdoubles as a cathode. FIG. 2(a), illustrates that the passing of currentcauses material 2 within the plating solution and material 2 from theanode 12 to be selectively transferred to and plated on the cathode 6.After electroplating the first deposition material 2 onto the substrate6 using CC mask 8, the CC mask 8 is removed as shown in FIG. 2(b). FIG.2(c) depicts the second deposition material 4 as having beenblanket-deposited (i.e. non-selectively deposited) over the previouslydeposited first deposition material 2 as well as over the other portionsof the substrate 6. The blanket deposition occurs by electroplating froman anode (not shown), composed of the second material, through anappropriate plating solution (not shown), and to the cathode/substrate6. The entire two-material layer is then planarized to achieve precisethickness and flatness as shown in FIG. 2(d). After repetition of thisprocess for all layers, the multi-layer structure 20 formed of thesecond material 4 (i.e. structural material) is embedded in firstmaterial 2 (i.e. sacrificial material) as shown in FIG. 2(e). Theembedded structure is etched to yield the desired device, i.e. structure20, as shown in FIG. 2(f).

[0028] Various components of an exemplary manual electrochemicalfabrication system 32 are shown in FIGS. 3(a)-3(c). The system 32consists of several subsystems 34, 36, 38, and 40. The substrate holdingsubsystem 34 is depicted in the upper portions of each of FIGS. 3(a) to3(c) and includes several components: (1) a carrier 48, (2) a metalsubstrate 6 onto which the layers are deposited, and (3) a linear slide42 capable of moving the substrate 6 up and down relative to the carrier48 in response to drive force from actuator 44. Subsystem 34 alsoincludes an indicator 46 for measuring differences in vertical positionof the substrate which may be used in setting or determining layerthicknesses and/or deposition thicknesses. The subsystem 34 furtherincludes feet 68 for carrier 48 which can be precisely mounted onsubsystem 36.

[0029] The CC mask subsystem 36 shown in the lower portion of FIG. 3(a)includes several components: (1) a CC mask 8 that is actually made up ofa number of CC masks (i.e. submasks) that share a common support/anode12, (2) precision X-stage 54, (3) precision Y-stage 56, (4) frame 72 onwhich the feet 68 of subsystem 34 can mount, and (5) a tank 58 forcontaining the electrolyte 16. Subsystems 34 and 36 also includeappropriate electrical connections (not shown) for connecting to anappropriate power source for driving the CC masking process.

[0030] The blanket deposition subsystem 38 is shown in the lower portionof FIG. 3(b) and includes several components: (1) an anode 62, (2) anelectrolyte tank 64 for holding plating solution 66, and (3) frame 74 onwhich the feet 68 of subsystem 34 may sit. Subsystem 38 also includesappropriate electrical connections (not shown) for connecting the anodeto an appropriate power supply for driving the blanket depositionprocess.

[0031] The planarization subsystem 40 is shown in the lower portion ofFIG. 3(c) and includes a lapping plate 52 and associated motion andcontrol systems (not shown) for planarizing the depositions.

[0032] In addition to the above teachings, the '630 patent sets forth aprocess for integrating EFAB production with integrated circuits. Inthis process the structural EFAB material is plated onto and inelectrical contact with aluminum contact pads on the integrated circuit.These contact pads may be considered primary contact pads and thelocations to which contact with the EFAB structural material will bemade. In the described process the integrated circuit design is modifiedto include secondary contact pads (i.e. one or more pads) that areelectrically connected to the primary pads but are spaced therefrom by adistance. The secondary contact pads provide connection points forfeeding current to the primary contact pads so that the primary pads mayfunction as cathodes during electroplating operations. The process isillustrated in FIGS. 13a-13 i of that patent and is outlined as follows:

[0033] 1. The process starts with

[0034] a. An integrated circuit that includes a silicon wafer 38, aprimary contact pad 40, and a secondary contact pad 41 connected to theprimary pad by conductor 42. With the exception of the contact pads 40and 41 the integrated circuit is covered by passivation layer 44 (FIGS.13a & 13 b); and

[0035] b. A polyimide 34 coated copper disk 36. The polyimide may becoated onto the disk by spin coating.

[0036] 2. The copper disk 36 is adhered to the bottom surface of thesilicon wafer 38 with the polyimide 34 coated surface of the copper disklocated between the copper and the silicon.

[0037] 3. The silicon wafer is partially sawed through which assists inseparation of the die after processing.

[0038] 4. A photosensitive polyimide 35 is spin coated onto the topsurface of wafer 38. This coating provides an additional passivationlayer and potentially protects aluminum pads 40 and 41 during subsequentetching operations and it fills saw line 46.

[0039] 5. The polyimide 35 is patterned by selective exposure to lightand subsequent development to expose contact pads 40 and 41.

[0040] 6. The wafer is degreased and immersed in zincate platingsolution which provides a thin coating over the exposed aluminum contactpads to increase adhesion of subsequently deposited material.

[0041] 7. A photoresist is applied and patterned leaving a valley intowhich copper may be deposited to form a bus 48 that connects contactpads 41 (FIG. 13d). Copper is deposited, for example by sputtering andthe photoresist is removed leaving behind copper bus 48.

[0042] 8. A photoresist is applied and patterned to cover most of bus 48to prevent nickel from depositing thereon.

[0043] 9. Electrical contact is made with the portion of the bus 48 thatis not covered by photoresist and then plating enough nickel 50 (FIG.13e) on aluminum pad 40 to allow subsequent planarization.

[0044] 10. The photoresist is removed thereby exposing the entire copperbus 48.

[0045] 11. A thin plating base of copper 51 is deposited, e.g. bysputtering, over the entire surface of the integrated circuit.

[0046] 12. Electrical contact is made with the copper and a sufficientamount of copper 52 is then electroplated over the entire wafer surfaceto allow planarization (FIG. 13F).

[0047] 13. The surface is planarized to expose the nickel 50 (FIG. 13g).

[0048] 14. Layers of the microstructure are electroplated (FIG. 13h).

[0049] 15. The copper deposited by electroplating and sputtering isremoved by etching.

[0050] 16. The polyimide 35 is stripped thereby exposing the resultingmicrostructure device 54 attached to wafer 38 (FIG. 13i).

[0051] Another method for forming microstructures from electroplatedmetals (i.e. using electrochemical fabrication techniques) is taught inU.S. Pat. No. 5,190,637 to Henry Guckel, entitled “Formation ofMicrostructures by Multiple Level Deep X-ray Lithography withSacrificial Metal layers. This patent teaches the formation of metalstructure utilizing mask exposures. A first layer of a primary metal iselectroplated onto an exposed plating base to fill a void in aphotoresist, the photoresist is then removed and a secondary metal iselectroplated over the first layer and over the plating base. Theexposed surface of the secondary metal is then machined down to a heightwhich exposes the first metal to produce a flat uniform surfaceextending across the both the primary and secondary metals. Formation ofa second layer may then begin by applying a photoresist layer over thefirst layer and then repeating the process used to produce the firstlayer. The process is then repeated until the entire structure is formedand the secondary metal is removed by etching. The photoresist is formedover the plating base or previous layer by casting and the voids in thephotoresist are formed by exposure of the photoresist through apatterned mask via X-rays or UV radiation.

[0052] Even in view of these teachings a need remains in theelectrochemical fabrication arts for alternative processes and simplerprocesses for integrating electrochemically fabricated structures withintegrated circuits and particularly for processes that allow formationof multilayer electrochemically fabricated structures on and inelectrical contact with semiconductor produced circuitry.

SUMMARY OF THE INVENTION

[0053] It is an object of various aspects of the present invention toprovide alternative processes for integrating electrochemicallyfabricated multilayer structures with integrated circuits.

[0054] It is an object of various aspects of the present invention toprovide simpler processes for integrating electrochemically fabricatedmultilayer structures with integrated circuits.

[0055] It is an object of various aspects of the present invention toprovide simpler processes that allow formation of multilayerelectrochemically fabricated structure on and in electrical contact withsemiconductor produced circuitry.

[0056] Other objects and advantages of various aspects of the inventionwill be apparent to those of skill in the art upon review of theteachings herein. The various aspects of the invention, set forthexplicitly herein or otherwise ascertained from the teachings herein,may address any one of the above objects alone or in combination, oralternatively may not address any of the objects set forth above butinstead address some other object ascertained from the teachings herein.It is not intended that all of these objects be addressed by any singleaspect of the invention even though that may be the case with regard tosome aspects.

[0057] A first aspect of the invention provides an electrochemicalfabrication process for producing a three-dimensional structure from aplurality of adhered layers, the process including: (A) selectivelydepositing at least a portion of a layer onto the substrate, wherein thesubstrate may include previously deposited material; (B) forming aplurality of layers such that successive layers are formed adjacent toand adhered to previously deposited layers, wherein said formingincludes repeating operation (A) a plurality of times; wherein at leasta plurality of the selective depositing operations include: (1) locatinga mask on or in proximity to a substrate; (2) in presence of a platingsolution, conducting an electric current between an anode and thesubstrate through the at least one opening in the mask, such that aselected deposition material is deposited onto the substrate to form atleast a portion of a layer; and (3) separating the selected preformedmask from the substrate; wherein the substrate includes a semiconductorwafer or single die containing electrical circuitry and having contactpads to which structural material is to connect; and wherein the processof contacting the contact pads with structural material includes inorder: (a) placing a protective coating over the contact pads; (b)applying a layer of sacrificial material to a surface of the wafer, (c)removing the protective coating from the contact pads; and (d) applyinga coating of structural material to the contact pads.

[0058] A second aspect of the invention provides an electrochemicalfabrication process for producing a three-dimensional structure from aplurality of adhered layers, the process including: (A) selectivelydepositing at least a portion of a layer onto the substrate, wherein thesubstrate may include previously deposited material; (B) forming aplurality of layers such that successive layers are formed adjacent toand adhered to previously deposited layers, wherein said formingincludes repeating operation (A) a plurality of times; wherein at leasta plurality of the selective depositing operations include: (1) locatinga mask on or in proximity to a substrate; (2) in presence of a platingsolution, conducting an electric current between an anode and thesubstrate through the at least one opening in the mask, such that aselected deposition material is deposited onto the substrate to form atleast a portion of a layer; and (3) separating the selected preformedmask from the substrate; wherein the substrate includes a semiconductorwafer or single die containing electrical circuitry and having contactpads to which structural material is to connect; and wherein the processof contacting the contact pads with structural material includes, inorder: (a) depositing sacrificial material onto a surface of the waferor die in regions excluding contact pad regions; and (b) depositingstructural material to at least selected contact pad regions.

[0059] A third aspect of the invention provides an electrochemicalfabrication process for producing a three-dimensional structure from aplurality of adhered layers, the process including: (A) selectivelydepositing at least a portion of a layer onto the substrate, wherein thesubstrate may include previously deposited material; (B) forming aplurality of layers such that successive layers are formed adjacent toand adhered to previously deposited layers, wherein said formingincludes repeating operation (A) a plurality of times; wherein at leasta plurality of the selective depositing operations include: (1) locatinga mask on or in proximity to a substrate; (2) in presence of a platingsolution, conducting an electric current between an anode and thesubstrate through the at least one opening in the mask, such that aselected deposition material is deposited onto the substrate to form atleast a portion of a layer; and (3) separating the selected preformedmask from the substrate; wherein the substrate includes a semiconductorwafer or single die containing electrical circuitry and having contactpads to which structural material is to connect and having a passivationlayer; and wherein the process of contacting the contact pads withstructural material includes in order: (a) locating an electrolessplating catalyst for a sacrificial material on at least a portion of thesurface of the passivation layer; (b) electroless plating thesacrificial material on to the passivation layer; (c) applying astructural material over the contact pads.

[0060] Further aspects of the invention will be understood by those ofskill in the art upon reviewing the teachings herein. Other aspects ofthe invention may involve combinations of the above noted aspects of theinvention and/or addition of various feat.3ures of one or moreembodiments. Other aspects of the invention may involve apparatus thatcan be used in implementing one or more of the above method aspects ofthe invention. These other aspects of the invention may provide variouscombinations of the aspects presented above as well as provide otherconfigurations, structures, functional relationships, and processes thathave not been specifically set forth above.

BRIEF DESCRIPTION OF THE DRAWINGS

[0061] FIGS. 1(a)-1(c) schematically depict side views of various stagesof a CC mask plating process, while FIGS. 1(d)-(g) schematically depicta side views of various stages of a CC mask plating process using adifferent type of CC mask.

[0062] FIGS. 2(a)-2(f) schematically depict side views of various stagesof an electrochemical fabrication process as applied to the formation ofa particular structure where a sacrificial material is selectivelydeposited while a structural material is blanket deposited.

[0063] FIGS. 3(a)-3(c) schematically depict side views of variousexample subassemblies that may be used in manually implementing theelectrochemical fabrication method depicted in FIGS. 2(a)-2(f).

[0064] FIGS. 4(a)-4(i) schematically depict the formation of a firstlayer of a structure using adhered mask plating where the blanketdeposition of a second material overlays both the openings betweendeposition locations of a first material and the first material itself.

[0065] FIGS. 5(a)-5(l) schematically depict side views of various stagesof a process according to a first embodiment for formingelectrochemically fabricated structures on integrated circuits.

[0066] FIGS. 6(a)-6(f) schematically depict side views of various stagesof a process according to one variation of a second embodiment forforming electrochemically fabricated structures on integrated circuits.

DETAILED DESCRIPTION

[0067] FIGS. 1(a)-1(g), 2(a)-2(f), and 3(a)-3(c) illustrate variousfeatures of one form of electrochemical fabrication that are known.Other electrochemical fabrication techniques are set forth in the '630patent referenced above, in the various previously incorporatedpublications, in various other patents and patent applicationsincorporated herein by reference, still others may be derived fromcombinations of various approaches described in these publications,patents, and applications, or are otherwise known or ascertainable bythose of skill in the art from the teachings set forth herein. All ofthese techniques may be combined with those of the various embodimentsof various aspects of the invention to yield enhanced embodiments. Stillother embodiments may be derived from combinations of the variousembodiments explicitly set forth herein.

[0068] FIGS. 4(a)-4(i) illustrate various stages in the formation of asingle layer of a multilayer fabrication process where a second metal isdeposited on a first metal as well as in openings in the first metalwhere its deposition forms part of the layer. In FIG. 4(a), a side viewof a substrate 82 is shown, onto which patternable photoresist 84 iscast as shown in FIG. 4(b). In FIG. 4(c), a pattern of resist is shownthat results from the curing, exposing, and developing of the resist.The patterning of the photoresist 84 results in openings or apertures92(a)-92(c) extending from a surface 86 of the photoresist through thethickness of the photoresist to surface 88 of the substrate 82. In FIG.4(d), a metal 94 (e.g. nickel) is shown as having been electroplatedinto the openings 92(a)-92(c). In FIG. 4(e), the photoresist has beenremoved (i.e. chemically stripped) from the substrate to expose regionsof the substrate 82 which are not covered with the first metal 94. InFIG. 4(f), a second metal 96 (e.g., silver) is shown as having beenblanket electroplated over the entire exposed portions of the substrate82 (which is conductive) and over the first metal 94 (which is alsoconductive). FIG. 4(g) depicts the completed first layer of thestructure which has resulted from the planarization of the first andsecond metals down to a height that exposes the first metal and sets athickness for the first layer. In FIG. 4(h) the result of repeating theprocess steps shown in FIGS. 4(b)-4(g) several times to form amulti-layer structure are shown where each layer consists of twomaterials. For most applications, one of these materials is removed asshown in FIG. 4(i) to yield a desired 3-D structure 98 (e.g. componentor device).

[0069] The various electrochemical fabrication processes used in variousembodiments, alternatives, and techniques disclosed herein may haveapplication to conformable contact masks and masking operations,proximity masks and masking operations (i.e. operations that use masksthat at least partially selectively shield a substrate by theirproximity to the substrate even if contact is not made), non-conformablemasks and masking operations (i.e. masks and operations based on maskswhose contact surfaces are not significantly conformable), and adheredmasks and masking operations (masks and operations that use masks thatare adhered to a substrate onto which selective deposition or etching isto occur as opposed to only being contacted to it).

[0070] Various embodiments are directed to techniques for interfacing orintegrating the electrochemical fabrication of multi-layer threedimensional structures with semiconductor devices (e.g. integratedcircuits) or devices produced by semiconductor manufacturing techniques.In the various embodiments presented hereafter, the semiconductordevices are provided in wafer form or die form and are used assubstrates for the electrochemical fabrication build up process. Thesedevices may be supplied with a passivation layer of adequate thicknessalready applied or such layers may be thickened prior to beginning theintegration process.

[0071] An integration process of a first preferred embodiment isdepicted in FIGS. 5(a)-5(l). A wafer 102 (or single die) is receivedfrom a standard IC fabrication process as shown in FIG. 5(a). The waferincludes electronic circuitry (not shown) with interface contact pads104 and connected bus contact pads 106 exposed. The pads are connectedby runners 108 which travel under a passivation layer 112 which coversthe surface of the wafer 102. Pads 104 and runners 108 may have beenspecifically designed with the intent of integrating a device made byelectrochemical fabrication, or alternatively pre-designed pads andinterconnects that can serve as runners may be used. Other pads (notshown) may be located on wafer 102 for purposes of wire bonding, flipchip packaging, etc.

[0072] A photoresist layer 122 is applied to the upper surface of thewafer as shown in FIG. 5(b). The photoresist is patterned so that theinterface pads 104 remain covered with hardened photoresist 124 as shownin FIG. 5(c). These covered pads are the ones to which the multilayerelectrochemically fabricated structure will be interfaced.

[0073] A thin layer of copper 126 is deposited over the entire surfaceas shown in FIG. 5(d). The deposition of the copper may for exampleoccur via a physical vapor deposition process (e.g. evaporated orsputtered), via electroless copper plating, or via direct metallization(i.e. direct plating). As the adhesion between the copper and theexposed aluminum bus contact pads is not critical it may be unnecessaryto apply a coating of zincate to the surface prior to copper deposition.But a zincate coating can be applied if desired or found necessary.Furthermore, as the bus contact pads 106 are located some distance fromthe interface contact pads, some damage by the copper to the bus contactpads may be acceptable. If such damage is a concern or found to be aproblem a barrier layer can be applied prior to the copper deposition.The barrier layer can then be removed toward the end of the processafter removal of the copper.

[0074] Next, electrical contact is made to the thin copper coating 126and thick copper 128 is plated as shown in FIG. 5(e) with a sufficientdepth to allow planarization to occur.

[0075] Next the applied coatings of copper are planarized to expose theresist 124 overlaying the interface contact pads 104 as shown in FIG.5(f). The resist 124 is then removed as shown in FIG. 5(g).

[0076] Next, a transition/barrier layer 132 is deposited onto the waferas shown in FIG. 5(h). The transition/barrier layer may include one orboth of a coating of an adhesion promoter (such as zincate) and adiffusion barrier such as titanium nitride (TiN), tantalum (Ta), and/ortantalum Nitride (TaN).

[0077] Next, electrical contact is made to the barrier layer and anelectrochemical fabrication structural material 134 (e.g., Ni) is platedthickly as shown in FIG. 5(i).

[0078] The deposits are again planarized as shown FIG. 5(j) exposing thethickly plated copper 128, and removing the barrier layer 132 exceptnear where it bounds the remaining nickel deposit 134 near the interfacecontact pads 104.

[0079] After again making electrical contact with the deposited metal,the electrochemical fabrication process is performed to build up themultiple layers of the three dimensional structure. The multilayerdeposition process is shown as completed in FIG. 5(k). Theelectrochemical fabrication process may be performed in a variety ofmanners and may include a variety of operations, such as, for example,selective depositions, selective etchings, blanket depositions, blanketetchings, planarization operations, and the like. It may also includevarious cleaning, activation, passivation, and other treatmentoperations. The selection of operations and the ordering of theoperations may vary from build process to build process or even fromlayer-to-layer within a single build process. Any selective depositionoperations, selective etching operations, or selective treatmentoperations may make use of contact masks (e.g. of the conformable ornon-conformable type), proximity masks, and/or adhered masks.

[0080] Next, all of the deposited copper is removed by etching asindicated in FIG. 5(l). Only the structural material from theelectrochemical fabrication process is left behind along with thetransition/barrier layer and the wafer or (single die) materialdeposited between the nickel and interface contact pads 104 and coveringa portion of the sides of the nickel around the interface contact pads.In this way the structure produced by electrochemical fabrication ismechanically and electrically interfaced to the metallization of thewafer.

[0081] Various alternatives to this first embodiment are possible. Forexample, a diffusion barrier layer could be deposited prior to the thincopper deposit 126 but after formation of the patterned resist 124, itcould be removed by controlled etching as its surface area would belargely exposed compared to the amount of exposure that a coatingbetween the interface contact pads 104 and the electrochemicallyfabricated structure would have. Due to this differential in exposure,it is believed that controlled etching may be performed, after layerformation is complete and the sacrificial material has been removed, toremove the barrier/transition layer from non-contact regions of theelectrochemically fabricated structure without excessive damage to thecontact regions after layer formation.

[0082] In another alternative embodiment, a barrier layer could beapplied prior to the application of the photoresist thereby obviatingthe need for a potential barrier layer prior to thin copper depositionof FIG. 5(d) and prior to the structural material deposition of FIG.5(i). In this alternative the uncovered portion of the barrier layerwould be removed after the removal of the copper.

[0083] In other alternative embodiments an adhesion transition layer mayalso be formed at different stages of the process.

[0084] In another alternative embodiment the runner and bus pad wouldnot be needed. In this alternative, the interface pad is made largerthan the area intended for deposition of the structural material (e.g.Ni). In this alternative, the portion of the interface contact pad 104that is not covered by the structural material serves as the contact pad(rather than having a remote contact pad). However, since Almetallization used in the integrated circuit device may be attacked bythe Cu stripper, etching of the Cu surrounding the structural materialmay damage the pad near the structural material. Using the runner andremote contact pad avoids this problem. Also this alternative embodimentcould benefit from the previous alternative embodiment where thepre-photoresist application of a barrier layer would inhibit the attack.

[0085] A second group of embodiments may take an alternative approach tointerfacing the wafer 102 to the initial conductive deposits onto whichthe multiple layers of the structure will be formed. FIGS. 6(a)-6(f)show one variation of the second group of embodiments. FIG. 6(a) showswafer 102 which may be prepared for the interfacing process by, forexample, coating pads 140 with a material that facilitateselectrodeposition or enhances adhesion (e.g., zincate treatment foraluminum pads) or adding additional passivation or barrier layers toprotect wafer 102 from materials (e.g., sodium) which may be present inplating or etching baths. In FIG. 6(b), a catalyst 142 for anelectroless plating bath that is suitable for depositing the sacrificialmaterial has been applied to the surface of the IC passivation layer112. Catalyst 142 may be selectively located on the passivation layeraway from contact pads 140 so that sacrificial material will not beinadvertently deposited onto the contact pads. However, if catalyst 142coats only the perimeter of pads 140 this is acceptable and may bedesirable in some embodiments. Catalyst 142 may be selectively applied,for example, by contacting the protruding surface of passivation 112with a plate or stamp coated with a thin film of catalyst 142, or byselectively dispensing catalyst 142 (e.g. via an ink jet or an extrusionhead).

[0086] In FIG. 6(c), sacrificial material 144 has been deposited ontothe catalyzed surface, which is assumed to be confined to the topsurface of passivation 112. In FIG. 6(d) the deposit has been continueduntil material 144 ‘mushrooms’ out and makes contact with the perimeterof pads 140. Once such contact is made, pads 140 are in electricalcontact with one another and with material 144 and can beelectrodeposited with another material. In FIG. 6(e), structuralmaterial has been electrodeposited onto pads 140. Finally, in FIG. 6(f),sacrificial and structural materials have been planarized so as tocreate a relatively flat and smooth substrate—as in FIG. 5(j)—suitableas a starting layer for further electrochemical fabrication operationswhere the starting layer includes regions of sacrificial material (e.g.,copper) and regions of structural material (e.g., nickel). In otherwords, the starting layer includes a structural material in regions thatcontact the pads and are intended to be electrically active, while atemporary presence of copper is located in all other regions.

[0087] An integration process of a first preferred embodiment isdepicted in FIGS. 5(a)-5(l). A wafer 102 (or single die) is receivedfrom a standard IC fabrication process as shown in FIG. 5(a). The waferincludes electronic circuitry (not shown) with interface contact pads104 and connected bus contact pads 106 exposed. The pads are connectedby runners 108 which travel under a passivation layer 112 which coversthe surface of the wafer 102.

[0088] A photoresist layer 122 is applied to the upper surface of thewafer as shown in FIG. 5(b). The photoresist is patterned so that theinterface pads 104 remained covered with hardened photoresist 124 asshown in FIG. 5(c). These covered pads are the ones to which themultilayer electrochemically fabricated structure will be interfaced.

[0089] A thin layer of copper 126 is deposited over the entire surfaceas shown in FIG. 5(d). The deposition of the copper may for exampleoccur via a physical vapor deposition process (e.g. evaporated orsputtered) or electroless copper plating. As the adhesion between thecopper and the exposed aluminum bus contact pads is not critical it maybe unnecessary to apply a coating of zincate to the surface prior tocopper deposition. But a Zincate coating can be applied is desired orfound necessary. Furthermore, as the bus contact pads 106 are locatedsome distance from the interface contact pads, some damage by the copperto the bus contact pads may be acceptable. If such damage is a concernor found to be a problem a barrier layer can be applied prior to thecopper deposition. The barrier layer can then be removed toward the endof the process after removal of the copper.

[0090] Next, electrical contact is made to the thin copper coating 126and thick copper 128 is plated as shown in FIG. 5.(e) with a sufficientdepth to allow planarization to occur.

[0091] Next the applied coatings of copper are planarized to expose theresist overlaying the interface contact pads 104 as shown in FIG. 5(f).The resist is then removed as shown in FIG. 5(g).

[0092] Next, a transition/barrier layer 132 is deposited onto the waferas shown in FIG. 5(h). The transition/barrier layer may include one orboth of a coating of an adhesion promoter (such as zincate) amid adiffusion barrier such as titanium nitride (TiN), tantalum (Ta), and/ortantalum Nitride (TaN).

[0093] Next, electrical contact is made to the barrier layer and anelectrochemical fabrication structural material 134 (e.g., Ni) is platedthickly as shown in FIG. 5(i).

[0094] Though the present embodiments have focused on electrochemicallyfabricated structures containing a structural material of nickel and asacrificial material of copper, other embodiments are possible wheredifferent structural and/or sacrificial materials are used. Furthermore,interfacing between a wafer or die and electrochemically producedstructures utilizing different structural and/or sacrificial materialsmay occur via the nickel and copper materials exemplified herein or mayoccur via the different materials according to the generalizedapplicability of the processes set forth herein to those materials.Still other embodiments will be apparent to those of skill in the artupon reviewing the teaching herein, such as processes that involvesvarious combinations of the operations used in the different embodimentsdisclosed herein.

[0095] Various alternatives to and variations of the above notedembodiments exist. In some alternative embodiments, the structuralmaterial of choice is nickel and the sacrificial material of choice iscopper, and in other embodiments other or additional structuralmaterials may be chosen and other or additional sacrificial materialsmay be chosen.

[0096] Various other embodiments exist. Some of these embodiments may bebased on a combination of the teachings herein with various teachingsincorporated herein by reference. Some embodiments may not use anyblanket deposition process and/or they may not use a planarizationprocess. Some embodiments may involve the selective deposition of aplurality of different materials on a single layer or on differentlayers. Some embodiments may use blanket depositions processes that arenot electrodeposition processes. Some embodiments may use selectivedeposition processes on some layers that are not conformable contactmasking processes and are not even electrodeposition processes. Someembodiments may use nickel as a structural material while otherembodiments may use different materials such as gold, silver, or anyother electrodepositable materials that can be separated from the copperand/or some other sacrificial material. Some embodiments may use copperas the structural material with or without a sacrificial material. Someembodiments may remove a sacrificial material while other embodimentsmay not. In some embodiments the anode may be different from theconformable contact mask support and the support may be a porousstructure or other perforated structure. Some embodiments may usemultiple conformable contact masks with different patterns so as todeposit different selective patterns of material on different layersand/or on different portions of a single layer. In some embodiments, thedepth of deposition will be enhanced by pulling the conformable contactmask away from the substrate as deposition is occurring in a manner thatallows the seal between the conformable portion of the CC mask and thesubstrate to shift from the face of the conformal material to the insideedges of the conformable material.

[0097] In view of the teachings herein, many further embodiments,alternatives in design and uses of the invention will be apparent tothose of skill in the art. As such, it is not intended that theinvention be limited to the particular illustrative embodiments,alternatives, and uses described above but instead that it be solelylimited by the claims presented hereafter.

I claim:
 1. An electrochemical fabrication process for producing a three-dimensional structure from a plurality of adhered layers, the process comprising: (A) selectively depositing at least a portion of a layer onto the substrate, wherein the substrate may comprise previously deposited material; (B) forming a plurality of layers such that successive layers are formed adjacent to and adhered to previously deposited layers, wherein said forming comprises repeating operation (A) a plurality of times; wherein at least a plurality of the selective depositing operations comprise: (1) locating a mask on or in proximity to a substrate; (2) in presence of a plating solution, conducting an electric current between an anode and the substrate through the at least one opening in the mask, such that a selected deposition material is deposited onto the substrate to form at least a portion of a layer; and (3) separating the selected preformed mask from the substrate; wherein the substrate comprises a semiconductor wafer or single die containing electrical circuitry and having contact pads to which structural material is to connect; and wherein the process of contacting the contact pads with structural material comprises in order: (a) placing a protective coating over the contact pads; (b) applying a layer of sacrificial material to a surface of the wafer, (c) removing the protective coating from the contact pads; and (d) applying a coating of structural material to the contact pads.
 2. The process of claim 1 wherein a plurality of layers comprise at least one structural material and at least one sacrificial material.
 3. The process of claim 1 wherein the applied layer of sacrificial material is thin compared to a desired coating thickness, and wherein after operation (b) and before operation (c), the process additional comprises: (b2) thickening the thin layer to many times its original thickness via electroplating.
 4. The process of claim 3, wherein after performance of operation (b2) and before operation (c), the process additionally comprises: (b3) planarizing the sacrificial material and the protective coating.
 5. The process of claim 4, wherein after performance of operation (d), the process additionally comprises: (e) planarizing the structural and sacrificial materials.
 6. The process of claim 5, wherein after performance of operation (e), the process additionally comprises: (e) forming a plurality of layers comprising at least one structural material and at least one sacrificial material.
 7. The process of claim 1 additionally comprising: (A) supplying a plurality of preformed masks, wherein each mask comprises a patterned dielectric material that includes at least one opening through which deposition can take place during the formation of at least a portion of a layer, and wherein each mask comprises a support structure that supports the patterned dielectric material; and wherein the locating of a mask on or in proximity to a substrate comprises contacting the substrate and the dielectric material of a selected preformed mask.
 8. The process of claim 1 wherein the locating of a mask on or in proximity to a substrate comprises forming and adhering a patterned mask to the substrate.
 9. The process of claim 1 wherein prior to operation (d), the process further comprises applying a transition treatment to the contact pads.
 10. The process of claim 9 wherein transition treatment comprises application of an adhesion promoter.
 11. The process of claim 9 wherein transition treatment comprises application of a diffusion barrier.
 12. An electrochemical fabrication process for producing a three-dimensional structure from a plurality of adhered layers, the process comprising: (A) selectively depositing at least a portion of a layer onto the substrate, wherein the substrate may comprise previously deposited material; (B) forming a plurality of layers such that successive layers are formed adjacent to and adhered to previously deposited layers, wherein said forming comprises repeating operation (A) a plurality of times; wherein at least a plurality of the selective depositing operations comprise: (1) locating a mask on or in proximity to a substrate; (2) in presence of a plating solution, conducting an electric current between an anode and the substrate through the at least one opening in the mask, such that a selected deposition material is deposited onto the substrate to form at least a portion of a layer; and (3) separating the selected preformed mask from the substrate; wherein the substrate comprises a semiconductor wafer or single die containing electrical circuitry and having contact pads to which structural material is to connect; and wherein the process of contacting the contact pads with structural material comprises, in order: (a) depositing sacrificial material onto a surface of the wafer or die in regions excluding contact pad regions; and (b) depositing structural material to at least selected contact pad regions.
 13. The process of claim 12 wherein a plurality of layers comprise at least one structural material and at least one sacrificial material.
 14. The process of claim 12 wherein prior to performance of operation (a), the process additionally comprises placing a protective coating over the contact pads.
 15. The process of claim 14 wherein after performance of operation (a), the process additionally comprises: (a3) removing the protective coating from at least selected contact pads.
 16. The process of claim 14 wherein operation (a) comprises depositing sacrificial material to a thickness less than a desired thickness using a first deposition operation and then increasing the thickness of the deposited sacrificial material using a different deposition operation.
 17. The process of claim 16 wherein first deposition operation comprises something other than an electroplating operation and wherein the second deposition operation comprises at least an electroplating operation.
 18. The process of claim 12 wherein after depositing the sacrificial material and depositing the structural material, planarizing the deposited materials to yield a substrate comprising selective regions of sacrificial and structural material on to which additional layers of a structural material and a sacrificial material will be deposited.
 19. The process of claim 12 wherein the process further comprises applying a transition treatment to the contact pads.
 20. The process of claim 19 wherein transition treatment comprises application of an adhesion promoter.
 21. The process of claim 19 wherein transition treatment comprises application of a diffusion barrier.
 22. The process of claim 12 wherein the structural material comprises nickel.
 23. The process of claim 12 wherein the sacrificial material comprise copper.
 24. The process of claim 12 additionally comprising: (A) supplying a plurality of preformed masks, wherein each mask comprises a patterned dielectric material that includes at least one opening through which deposition can take place during the formation of at least a portion of a layer, and wherein each mask comprises a support structure that supports the patterned dielectric material; and wherein the locating of a mask on or in proximity to a substrate comprises contacting the substrate and the dielectric material of a selected preformed mask.
 25. The process of claim 12 wherein the locating of a mask on or in proximity to a substrate comprises forming and adhering a patterned mask to the substrate.
 26. An electrochemical fabrication process for producing a three-dimensional structure from a plurality of adhered layers, the process comprising: (A) selectively depositing at least a portion of a layer onto the substrate, wherein the substrate may comprise previously deposited material; (B) forming a plurality of layers such that successive layers are formed adjacent to and adhered to previously deposited layers, wherein said forming comprises repeating operation (A) a plurality of times; wherein at least a plurality of the selective depositing operations comprise: (1) locating a mask on or in proximity to a substrate; (2) in presence of a plating solution, conducting an electric current between an anode and the substrate through the at least one opening in the mask, such that a selected deposition material is deposited onto the substrate to form at least a portion of a layer; and (3) separating the selected preformed mask from the substrate; wherein the substrate comprises a semiconductor wafer or single die containing electrical circuitry and having contact pads to which structural material is to connect and having a passivation layer; and wherein the process of contacting the contact pads with structural material comprises in order: (a) locating an electroless plating catalyst for a sacrificial material on at least a portion of the surface of the passivation layer; (b) electroless plating the sacrificial material on to the passivation layer; (c) applying a structural material over the contact pads.
 27. The process of claim 26 wherein the sacrificial material comprises copper.
 28. The process of claim 26 wherein the structural material comprises nickel.
 29. The process of claim 26 wherein the applying of the structural material comprises electroplating the structural material.
 30. The process of claim 26 wherein after operation (b), the process additionally comprises: (b2) increasing the thickness of the sacrificial material by electroplating additional sacrificial material onto the electroless plated sacrificial material.
 31. The process of claim 26 wherein after operation (c), the process additionally comprises: (d) planarizing the deposited materials.
 32. The process of claim 26 wherein a plurality of layers comprise at least one structural material and at least one sacrificial material.
 33. The process of claim 26 additionally comprising: (A) supplying a plurality of preformed masks, wherein each mask comprises a patterned dielectric material that includes at least one opening through which deposition can take place during the formation of at least a portion of a layer, and wherein each mask comprises a support structure that supports the patterned dielectric material; and wherein the locating of a mask on or in proximity to a substrate comprises contacting the substrate and the dielectric material of a selected preformed mask.
 34. The process of claim 26 wherein the locating of a mask on or in proximity to a substrate comprises forming and adhering a patterned mask to the substrate. 